Parallelization of automotive engine control software on embedded multi-core processor using OSCAR compiler

Yohei Kanehagi, Dan Umeda, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

The next-generation automobiles are required to be more safe, comfortable and energy-efficient. These requirements can be realized by integrated control systems with enhanced electric control units, or real-time control system such as engine control and enhanced information system such as human and other cars recognition, navigations considering traffic conditions including the occasions of natural disasters. For example, sophisticating engine control algorithms requires performance enhancement of microprocessors to satisfy real-time constraints. Use of multi-core processors is a promising approach to realize the next-generation automobiles integrated control system. In terms of multi-core processors in the automotive control, the previous works include improvements of reliability by performing redundant calculation [1] and improvements of throughput by functional distribution [2] rather than improvement of response time, or performance by parallel processing. To the best of our knowledge, parallel processing of the automotive control software to reduce response time has not been succeeded on multi-core processors because the program consists of conditional branches and small basic blocks. On the other hand, this paper is the first paper has successfully parallelized the practical automotive engine control software using automatic multigrain parallelizing compiler, or the OSCAR Compiler has been developed by the authors for more than 25 years. The OSCAR compiler parallelizes automotive programs by utilizing coarse grain task parallelism with newly developed parallelism enhanced methods like the branch duplication instead of loop parallelism. Performance of the hand-written engine control programs provided by Toyota Motor Corp. on the RP-X having eight SH4A processor cores developed by Renesas, Hitachi, Tokyo Institute of technology and Waseda University is evaluated. The evaluation shows speedups of 1.54 times with 2 processor cores compared with the case of an ordinary sequential execution.

本文言語English
ホスト出版物のタイトルIEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI
DOI
出版ステータスPublished - 2013 8 15
イベント16th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2013 - Yokohama, Japan
継続期間: 2013 4 172013 4 19

出版物シリーズ

名前IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI

Conference

Conference16th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2013
CountryJapan
CityYokohama
Period13/4/1713/4/19

ASJC Scopus subject areas

  • Hardware and Architecture

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