Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

Kazunori Shimizu*, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

*この研究の対応する著者

研究成果: Conference contribution

30 被引用数 (Scopus)

抄録

This paper proposes a partially-parallel LDPC decoder based on a high-efficiency message-passing algorithm. Our proposed partially-parallel LDPC decoder performs the column operations for bit nodes in conjunction with the row operations for check nodes. Bit functional unit with pipeline architecture in our LDPC decoder allows us to perform column operations for every bit node connected to each of check nodes which are updated by the row operations in parallel. Our proposed LDPC decoder improves the timing when the column operations are performed, accordingly it improves the message-passing efficiency within the limited number of iterations for decoding. We implemented the proposed partially-parallel LDPC decoder on an FPGA, and simulated its decoding performance. Practical simulation shows that our proposed LDPC decoder reduces the number of iterations for decoding, and it improves the bit error performance with a small hardware overhead.

本文言語English
ホスト出版物のタイトルProceedings - 2005 IEEE International Conference on Computer Design
ホスト出版物のサブタイトルVLSI in Computers and Processors, ICCD 2005
ページ503-510
ページ数8
DOI
出版ステータスPublished - 2005 12月 1
イベント2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 - San Jose, CA, United States
継続期間: 2005 10月 22005 10月 5

出版物シリーズ

名前Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
2005
ISSN(印刷版)1063-6404

Conference

Conference2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005
国/地域United States
CitySan Jose, CA
Period05/10/205/10/5

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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