The technique of multiple supply voltages and dynamic frequency has been explored as a possible energy-efficient strategy in CMOS circuits. In this paper, we consider the technique in the scheduling process which is the keys of high level synthesis. Given a schedule, a novel method is presented for the frequency assignment. The objective is to decrease the energy consumption as much as possible without violating the timing constraints. Initially, an approach based on the convex cost integer network flow is proposed to generate a feasible initial frequency assignment solution. Secondly, a branch and bound method is used to improve the initial solution. Finally, due to the frequency assignment result, we perform the assignment of voltage to each function operation in the control steps. The experimental results show the effectiveness of the proposed method. It is observed that using three supply voltage levels (5V; 3.3V; 2.4V ), an average energy savings of 25% to 40% (with the time constraint of 1.5 to 2.0 times the critical path) is obtained as compared to using a single-frequency clocking scheme with a single supply voltage.
|ホスト出版物のタイトル||IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS|
|出版ステータス||Published - 2010|
|イベント||2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur|
継続期間: 2010 12月 6 → 2010 12月 9
|Other||2010 Asia Pacific Conference on Circuit and System, APCCAS 2010|
|Period||10/12/6 → 10/12/9|
ASJC Scopus subject areas