Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology

Hiroaki Suzuki*, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara

*この研究の対応する著者

研究成果: Conference contribution

抄録

The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technology era. The proposed platform measures device speed during post-fabrication testing. Then the fast die is marked so that the body-bias circuit turns on and reduces leakage current of the die that is selected and marked in a user application. Because the slow die around the speed specifications of a product is not body-biased, the product runs as fast as a normal non-body-biasing product. Although the leakage power of a fast die is reduced, the speed specification does not change. The proposed platform improves the worst corner specification comprising the two worst cases of speed and leakage power. The test chip, fabricated using 45-nm technology, improves the worst corner of stand-by leakage power vs. speed by 70%.

本文言語English
ホスト出版物のタイトルISLPED'08
ホスト出版物のサブタイトルProceedings of the 2008 International Symposium on Low Power Electronics and Design
ページ15-20
ページ数6
DOI
出版ステータスPublished - 2008 12月 17
外部発表はい
イベントISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design - Bangalore, India
継続期間: 2008 8月 112008 8月 13

出版物シリーズ

名前Proceedings of the International Symposium on Low Power Electronics and Design
ISSN(印刷版)1533-4678

Other

OtherISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design
国/地域India
CityBangalore
Period08/8/1108/8/13

ASJC Scopus subject areas

  • 工学(全般)

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