Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs

Taeko Matsunaga*, Shinji Kimura, Yusuke Matsunaga

*この研究の対応する著者

研究成果: Conference contribution

13 被引用数 (Scopus)

抄録

Recent researches have indicated that multi-operand addition on FPGAs can be efficiently realized as the architecture consisting of a compressor tree which reduces the number of operands and a carry-propagate adder like ASIC by utilizing generalized parallel counters(GPCs). This paper addresses power and delay aware synthesis of GPC-based compressor trees. Based on the observation that dynamic power would correlate to the number of GPCs and the levels of GPCs, our approach targets to minimize the maximum levels and the total number of GPCs, and an ILP-based algorithm and heuristic approaches are proposed. Several experiments targeting Altera Stratix III architecture show that the proposed approach reduced the delay by up to 20% under a slight increase in total power dissipation.

本文言語English
ホスト出版物のタイトルIEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
ページ217-222
ページ数6
DOI
出版ステータスPublished - 2011 9 19
イベント17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka, Japan
継続期間: 2011 8 12011 8 3

出版物シリーズ

名前Proceedings of the International Symposium on Low Power Electronics and Design
ISSN(印刷版)1533-4678

Other

Other17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
国/地域Japan
CityFukuoka
Period11/8/111/8/3

ASJC Scopus subject areas

  • 工学(全般)

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