Power and noise aware test using preliminary estimation

Kenji Noda*, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo

*この研究の対応する著者

研究成果: Conference contribution

10 被引用数 (Scopus)

抄録

Issues on power consumption and IR-drop in testing become serious problems. Some troubles, such as tester fails due to too much power consumption or IR-drop, test escapes due to slowed clock cycle, and so on, can happen in test floors. In this paper, we propose a power and noise aware scan test method. In the method, power-aware DFT and power-aware ATPG are executed based on the preliminary power/noise estimation for test. Experimental results illustrate the effect of reducing IR-drop for both shift and capture mode in scan test.

本文言語English
ホスト出版物のタイトル2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
ページ323-326
ページ数4
DOI
出版ステータスPublished - 2009
外部発表はい
イベント2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan, Province of China
継続期間: 2009 4月 282009 4月 30

出版物シリーズ

名前2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Conference

Conference2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
国/地域Taiwan, Province of China
CityHsinchu
Period09/4/2809/4/30

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 制御およびシステム工学
  • 電子工学および電気工学

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