Power-efficient and slew-aware three dimensional gated clock tree synthesis

研究成果: Conference contribution

8 被引用数 (Scopus)

抄録

This paper presents a three dimensional (3D) gated clock tree synthesis (CTS) approach, which consists of two steps: 1) abstract tree topology generation; and 2) 3D gated and buffered clock routing. 3D Pair Matching (3D-PM) algorithm is proposed to generate the initial tree topology and then the proposed TSV-minimization algorithm is applied to generate TSV-aware tree topology. Based on TSV-aware tree topology, 3D gated and buffered clock tree routing is done using the proposed 3D Gated and Buffered Deferred-Merge Embedding (3D-GB-DME) algorithm. The slew constraint satisfaction is considered and the clock skew is minimized in our approach. Experimental results show that the proposed method achieves 29.11% power reduction compared with the state-of-the-art 2D work.

本文言語English
ホスト出版物のタイトル2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781509035618
DOI
出版ステータスPublished - 2016 11 22
イベント24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016 - Tallinn, Estonia
継続期間: 2016 9 262016 9 28

Other

Other24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
国/地域Estonia
CityTallinn
Period16/9/2616/9/28

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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