Power-efficient LDPC code decoder architecture

Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

研究成果: Conference contribution

3 引用 (Scopus)

抜粋

This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression technique based on a clock gated shift register which reduces the read and write power dissipation for the intermediate messages. Simulation results show that the proposed decoder achieves 1.66 times faster decoding throughput, and improves the power efficiency (which is defined by the power dissipation per Mbps) up to 52% compared to the decoder based on the conventional overlapped schedule.

元の言語English
ホスト出版物のタイトルISLPED'07
ホスト出版物のサブタイトルProceedings of the 2007 International Symposium on Low Power Electronics and Design
ページ359-362
ページ数4
DOI
出版物ステータスPublished - 2007 12 17
イベントISLPED'07: 2007 International Symposium on Low Power Electronics and Design - Portland, OR, United States
継続期間: 2007 8 272007 8 29

出版物シリーズ

名前Proceedings of the International Symposium on Low Power Electronics and Design
ISSN(印刷物)1533-4678

Conference

ConferenceISLPED'07: 2007 International Symposium on Low Power Electronics and Design
United States
Portland, OR
期間07/8/2707/8/29

ASJC Scopus subject areas

  • Engineering(all)

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  • これを引用

    Shimizu, K., Togawa, N., Ikenaga, T., & Goto, S. (2007). Power-efficient LDPC code decoder architecture. : ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design (pp. 359-362). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/1283780.1283858