Power-efficient LDPC decoder architecture based on accelerated message-passing schedule

Kazunori Shimizu*, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

*この研究の対応する著者

研究成果: Article査読

5 被引用数 (Scopus)

抄録

In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port SRAMs. (ii) FIFO-based buffering reduces the number of SRAM banks and words of the LDPC decoder based on the accelerated message-passing schedule. The proposed LDPC decoder keeps a single message for each non-zero bit in a parity check matrix as well as a classical schedule while achieving the accelerated message-passing schedule. Implementation results in 0.18 μm] CMOS technology show that the proposed decoder architecture reduces an area of the LDPC decoder by 43 and a power dissipation by 29 compared to the conventional architecture based on the accelerated message-passing schedule.

本文言語English
ページ(範囲)3602-3612
ページ数11
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E89-A
12
DOI
出版ステータスPublished - 2006 12月

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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