Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation

Hiroki Koike*, Takashi Ohsawa, Sadahiko Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

*この研究の対応する著者

研究成果: Article査読

7 被引用数 (Scopus)

抄録

A spintronic-based power-gated micro-processing unit (MPU) is proposed. It includes a power control circuit activated by the newly supported power-off instruction for the deep-sleep mode. These means enable the power-off procedure for the MPU to be executed appropriately. A test chip was designed and fabricated using 90nm CMOS and an additional 100nm MTJ process; it was successfully operated. The guideline of the energy reduction effects for this MPU was presented, using the estimation based on the measurement results of the test chip. The result shows that a large operation energy reduction of 1/28 can be achieved when the operation duty is 10%, under the condition of a sufficient number of idle clock cycles.

本文言語English
論文番号04DE08
ジャーナルJapanese journal of applied physics
54
4
DOI
出版ステータスPublished - 2015 4月 1
外部発表はい

ASJC Scopus subject areas

  • 工学(全般)
  • 物理学および天文学(全般)

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