Power Reduction Controll for Multicores in OSCAR Multigrain Parallelizing Compiler

Jun Shirako*, Keiji Kimura, Hironori Kasahara

*この研究の対応する著者

研究成果: Conference contribution

抄録

Multicore processors have become mainstream computer architecture to go beyond the performance and powerefficiency limits of single-core processors. To achieve low power consumption and high performance on multicores, parallelizing compilers take on an important role. This paper describes the performance of a compiler-based power reduction scheme cooperating with OSCAR multigrain parallelizing compiler on a newly developed 8-way SH4A low power multicore chip for consumer electronics, which supports DVFS (Dynamic Voltage and Frequency Scaling) and Clock/Power Gating. Using hardware parameters and parallelized program information, OSCAR compiler determines suitable voltage and frequency of each active processor core and appropriate schedule of clock gating and power gating. Performance experiments shows the compiler reduces consumed power by 88.3%, namely from 5.68 W to 0.67 W, for real-time secure AAC Encoding and 73.5%, namely from 5.73 W to 1.52 W, for real-time MPEG2 Decoding on 8 core execution.

本文言語English
ホスト出版物のタイトル2008 International SoC Design Conference, ISOCC 2008
出版社IEEE Computer Society
ページ50-55
ページ数6
ISBN(印刷版)9781424425990
DOI
出版ステータスPublished - 2008
イベント2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of
継続期間: 2008 11 242008 11 25

出版物シリーズ

名前s2008 International SoC Design Conference, ISOCC 2008
1

Conference

Conference2008 International SoC Design Conference, ISOCC 2008
国/地域Korea, Republic of
CityBusan
Period08/11/2408/11/25

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • ソフトウェア

フィンガープリント

「Power Reduction Controll for Multicores in OSCAR Multigrain Parallelizing Compiler」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル