Power reduction through specific instruction scheduling based on hardware/software Co-design

Zhao Kang*, Bian Jinian, Jiang Chenqian, Dong Sheqin, Satoshi Goto

*この研究の対応する著者

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

In this paper, an instruction-level power reduction model for the low power System-on-a-Chip is proposed, which combines the hardware and software design together. Firstly, to reduce the power consumption via hardware design, this model is equipped with a specific instruction extraction process, which utilizes a sub-graph matching algorithm. Then a scheduling algorithm is integrated in this model to achieve power compression via reducing the memory access number. Finally, a set of Fir filter programs are power-driven optimized using the proposed model based on hardware/software co-design strategy, and the experimental results indicate that this model can reduce the power consumption effectively.

本文言語English
ホスト出版物のタイトルASICON 2007 - 2007 7th International Conference on ASIC Proceeding
ページ193-196
ページ数4
DOI
出版ステータスPublished - 2007
イベント2007 7th International Conference on ASIC, ASICON 2007 - Guilin
継続期間: 2007 10 262007 10 29

Other

Other2007 7th International Conference on ASIC, ASICON 2007
CityGuilin
Period07/10/2607/10/29

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

フィンガープリント

「Power reduction through specific instruction scheduling based on hardware/software Co-design」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル