In this paper, an instruction-level power reduction model for the low power System-on-a-Chip is proposed, which combines the hardware and software design together. Firstly, to reduce the power consumption via hardware design, this model is equipped with a specific instruction extraction process, which utilizes a sub-graph matching algorithm. Then a scheduling algorithm is integrated in this model to achieve power compression via reducing the memory access number. Finally, a set of Fir filter programs are power-driven optimized using the proposed model based on hardware/software co-design strategy, and the experimental results indicate that this model can reduce the power consumption effectively.
|ホスト出版物のタイトル||ASICON 2007 - 2007 7th International Conference on ASIC Proceeding|
|出版ステータス||Published - 2007|
|イベント||2007 7th International Conference on ASIC, ASICON 2007 - Guilin|
継続期間: 2007 10 26 → 2007 10 29
|Other||2007 7th International Conference on ASIC, ASICON 2007|
|Period||07/10/26 → 07/10/29|
ASJC Scopus subject areas