PRACTICAL STUDY ON THE ARCHITECTURE OF VLSI DSP.

Toshitaka Tsuda, Yukou Mochida

    研究成果: Article査読

    抄録

    The architecture of a pipelined multiplier is examined. The throughput of a 16-bit multiplier using fixed-point arithmetic is analyzed for a single-cycle structure, a 2-stage pipeline structure, and a 3-stage pipeline structure. The total efficiency, which includes overheads inherent to a pipeline structure, is examined for each structure for programs developed for practical applications such as a 32 kb/s SDPCM codec, an echo canceller, 19-section filter banks for voice recognition, etc. Each analysis showed that the 2-stage pipeline structure is a suitable choice from the viewpoints of efficiency and simplicity of programming.

    本文言語English
    ページ(範囲)2179-2182
    ページ数4
    ジャーナルUnknown Journal
    出版ステータスPublished - 1986

    ASJC Scopus subject areas

    • 信号処理
    • 電子工学および電気工学
    • 音響学および超音波学

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