Practically scalable floorplanning with voltage island generation

Song Chen*, Xiaolin Zhang, Takeshi Yoshimura

*この研究の対応する著者

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

In this paper, we propose a method of floorplanning with voltage island generation for system-on-chips (SoC) designs, which is deeply coupled with voltage island partitioning and voltage assignment, and has a good scalability. Floorplans with voltage islands are represented using nested Sequence Pairs, where the cores involved in the same voltage island consecutively appear in the sequences. Starting from a randomly generated initial floorplan, where each non chip-level core occupies an individual voltage island, we iteratively improve the solution by removing a core from the floorplan, then, inserting back the core by trying all the possible O(n 2) block positions, which are defined as the combinations of insertion points and voltage islands. An almost linear algorithm is devised to roughly but quickly filter many worse block positions, in each iteration, considering fixed-outline constraints, wirelength, power, power/ground routing resources, and level shifters. Compared with the latest work, the proposed method shows 9.74% and 21.04% improvements respectively on the wirelength and power when all the blocks are hard. When soft blocks are involved, the proposed method shows 12.38% wirelength reduction and 3.10% more power saving with a penalty of 7.5% whitespace. Moreover, more than 20X speedups can be obtained for the large test cases.

本文言語English
ホスト出版物のタイトルProceedings of the International Symposium on Low Power Electronics and Design
ページ27-32
ページ数6
DOI
出版ステータスPublished - 2012
イベント2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 - Redondo Beach, CA
継続期間: 2012 7 302012 8 1

Other

Other2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12
CityRedondo Beach, CA
Period12/7/3012/8/1

ASJC Scopus subject areas

  • 工学(全般)

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