Precise timing verification of logic circuits under combined delay model

Shinji Kimura, Shigemi Kashima, Hiromasa Haneda

研究成果: Conference contribution

抄録

The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuits including 100 elements or so.

元の言語English
ホスト出版物のタイトルIEEE/ACM International Conference on Computer-Aided Design
出版場所Los Alamitos, CA, United States
出版者Publ by IEEE
ページ526-529
ページ数4
ISBN(印刷物)0818630108
出版物ステータスPublished - 1992
外部発表Yes
イベントIEEE/ACM International Conference on Computer-Aided Design - ICCAD '92 - Santa Clara, CA, USA
継続期間: 1992 11 81992 11 12

Other

OtherIEEE/ACM International Conference on Computer-Aided Design - ICCAD '92
Santa Clara, CA, USA
期間92/11/892/11/12

Fingerprint

Logic circuits
Networks (circuits)
Time delay
Hazards

ASJC Scopus subject areas

  • Engineering(all)

これを引用

Kimura, S., Kashima, S., & Haneda, H. (1992). Precise timing verification of logic circuits under combined delay model. : IEEE/ACM International Conference on Computer-Aided Design (pp. 526-529). Los Alamitos, CA, United States: Publ by IEEE.

Precise timing verification of logic circuits under combined delay model. / Kimura, Shinji; Kashima, Shigemi; Haneda, Hiromasa.

IEEE/ACM International Conference on Computer-Aided Design. Los Alamitos, CA, United States : Publ by IEEE, 1992. p. 526-529.

研究成果: Conference contribution

Kimura, S, Kashima, S & Haneda, H 1992, Precise timing verification of logic circuits under combined delay model. : IEEE/ACM International Conference on Computer-Aided Design. Publ by IEEE, Los Alamitos, CA, United States, pp. 526-529, IEEE/ACM International Conference on Computer-Aided Design - ICCAD '92, Santa Clara, CA, USA, 92/11/8.
Kimura S, Kashima S, Haneda H. Precise timing verification of logic circuits under combined delay model. : IEEE/ACM International Conference on Computer-Aided Design. Los Alamitos, CA, United States: Publ by IEEE. 1992. p. 526-529
Kimura, Shinji ; Kashima, Shigemi ; Haneda, Hiromasa. / Precise timing verification of logic circuits under combined delay model. IEEE/ACM International Conference on Computer-Aided Design. Los Alamitos, CA, United States : Publ by IEEE, 1992. pp. 526-529
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