Precise timing verification of logic circuits under combined delay model

Shinji Kimura, Shigemi Kashima, Hiromasa Haneda

研究成果: Conference contribution

抜粋

The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuits including 100 elements or so.

元の言語English
ホスト出版物のタイトルIEEE/ACM International Conference on Computer-Aided Design
出版者Publ by IEEE
ページ526-529
ページ数4
ISBN(印刷物)0818630108
出版物ステータスPublished - 1992 12 1
イベントIEEE/ACM International Conference on Computer-Aided Design - ICCAD '92 - Santa Clara, CA, USA
継続期間: 1992 11 81992 11 12

出版物シリーズ

名前IEEE/ACM International Conference on Computer-Aided Design

Other

OtherIEEE/ACM International Conference on Computer-Aided Design - ICCAD '92
Santa Clara, CA, USA
期間92/11/892/11/12

    フィンガープリント

ASJC Scopus subject areas

  • Engineering(all)

これを引用

Kimura, S., Kashima, S., & Haneda, H. (1992). Precise timing verification of logic circuits under combined delay model. : IEEE/ACM International Conference on Computer-Aided Design (pp. 526-529). (IEEE/ACM International Conference on Computer-Aided Design). Publ by IEEE.