Preciseness of discrete time verification

Shinji Kimura, Shunsuke Tsubota, Hiromasa Haneda

研究成果: Article

抄録

The discrete time analysis of logic circuits is usually more efficient than the continuous time analysis, but the preciseness of the discrete time analysis is not guaranteed. The paper shows a method to decide a unit time for a logic circuit under which the analysis result is the same as the result based on the continuous time. The delay time of an element is specified with an interval between the minimum and maximum delay times, and we assume an analysis method which enumerates all possible delay cases under the discrete time. Our main theorem is as follows: refine the unit time by a factor of 1/2, and if the analysis result with a unit time u and that with a unit time u/2 are the same, then us is the expected unit time.

元の言語English
ページ(範囲)1755-1756
ページ数2
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E76-A
発行部数10
出版物ステータスPublished - 1993 10
外部発表Yes

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Logic circuits
Time delay
Discrete-time
Unit
Delay Time
Continuous Time
Logic
Interval
Theorem

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Electrical and Electronic Engineering

これを引用

Preciseness of discrete time verification. / Kimura, Shinji; Tsubota, Shunsuke; Haneda, Hiromasa.

:: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 巻 E76-A, 番号 10, 10.1993, p. 1755-1756.

研究成果: Article

Kimura, Shinji ; Tsubota, Shunsuke ; Haneda, Hiromasa. / Preciseness of discrete time verification. :: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 1993 ; 巻 E76-A, 番号 10. pp. 1755-1756.
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