### 抄録

The discrete time analysis of logic circuits is usually more efficient than the continuous time analysis, but the preciseness of the discrete time analysis is not guaranteed. The paper shows a method to decide a unit time for a logic circuit under which the analysis result is the same as the result based on the continuous time. The delay time of an element is specified with an interval between the minimum and maximum delay times, and we assume an analysis method which enumerates all possible delay cases under the discrete time. Our main theorem is as follows: refine the unit time by a factor of 1/2, and if the analysis result with a unit time u and that with a unit time u/2 are the same, then us is the expected unit time.

元の言語 | English |
---|---|

ページ（範囲） | 1755-1756 |

ページ数 | 2 |

ジャーナル | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |

巻 | E76-A |

発行部数 | 10 |

出版物ステータス | Published - 1993 10 |

外部発表 | Yes |

### Fingerprint

### ASJC Scopus subject areas

- Signal Processing
- Computer Graphics and Computer-Aided Design
- Applied Mathematics
- Electrical and Electronic Engineering

### これを引用

*IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences*,

*E76-A*(10), 1755-1756.

**Preciseness of discrete time verification.** / Kimura, Shinji; Tsubota, Shunsuke; Haneda, Hiromasa.

研究成果: Article

*IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences*, 巻. E76-A, 番号 10, pp. 1755-1756.

}

TY - JOUR

T1 - Preciseness of discrete time verification

AU - Kimura, Shinji

AU - Tsubota, Shunsuke

AU - Haneda, Hiromasa

PY - 1993/10

Y1 - 1993/10

N2 - The discrete time analysis of logic circuits is usually more efficient than the continuous time analysis, but the preciseness of the discrete time analysis is not guaranteed. The paper shows a method to decide a unit time for a logic circuit under which the analysis result is the same as the result based on the continuous time. The delay time of an element is specified with an interval between the minimum and maximum delay times, and we assume an analysis method which enumerates all possible delay cases under the discrete time. Our main theorem is as follows: refine the unit time by a factor of 1/2, and if the analysis result with a unit time u and that with a unit time u/2 are the same, then us is the expected unit time.

AB - The discrete time analysis of logic circuits is usually more efficient than the continuous time analysis, but the preciseness of the discrete time analysis is not guaranteed. The paper shows a method to decide a unit time for a logic circuit under which the analysis result is the same as the result based on the continuous time. The delay time of an element is specified with an interval between the minimum and maximum delay times, and we assume an analysis method which enumerates all possible delay cases under the discrete time. Our main theorem is as follows: refine the unit time by a factor of 1/2, and if the analysis result with a unit time u and that with a unit time u/2 are the same, then us is the expected unit time.

UR - http://www.scopus.com/inward/record.url?scp=0027685244&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027685244&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0027685244

VL - E76-A

SP - 1755

EP - 1756

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 10

ER -