抄録
Interconnect reduction is one of the key issues in high-level synthesis. In this paper, we propose a primal-dual based method to solve the functional unit (FU) and register binding simultaneously while minimizing the global interconnection. Specifically, the binding problem is formulated as a min-cost network flow based on splitting weighted and order compatibility graphs (SWOCGs). The interconnect sharing among registers and FUs are maximized by binding the the operations or variables on the same path to the same FUs or registers according to the flow. Experimental results show that, compared with the previous greedy method [7], our proposed algorithm achieves an average 4.8% further reduction in global interconnection for a suite of benchmarks.
本文言語 | English |
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ホスト出版物のタイトル | Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 |
出版社 | Institute of Electrical and Electronics Engineers Inc. |
ISBN(電子版) | 9781479984831 |
DOI | |
出版ステータス | Published - 2016 7月 19 |
イベント | 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China 継続期間: 2015 11月 3 → 2015 11月 6 |
Other
Other | 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 |
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国/地域 | China |
City | Chengdu |
Period | 15/11/3 → 15/11/6 |
ASJC Scopus subject areas
- ハードウェアとアーキテクチャ
- 電子工学および電気工学