A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.
|ジャーナル||IEEE Transactions on Electron Devices|
|出版物ステータス||Published - 1987 12 1|
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering