A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.
|ジャーナル||IEEE Transactions on Electron Devices|
|出版ステータス||Published - 1987 12月 1|
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