PROCESS FOR A CMOS CHANNEL-STOP IMPLANTATION SELF-ALIGNED TO THE P-WELL AND P-WELL ACTIVE AREA.

Noriyoshi Yamauchi

研究成果: Article査読

抄録

A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.

本文言語English
ジャーナルIEEE Transactions on Electron Devices
ED-34
12
出版ステータスPublished - 1987 12 1
外部発表はい

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

フィンガープリント 「PROCESS FOR A CMOS CHANNEL-STOP IMPLANTATION SELF-ALIGNED TO THE P-WELL AND P-WELL ACTIVE AREA.」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル