Process integration of fine pitch Cu redistribution wiring and SnCu micro-bumping for power efficient LSI devices with high-bandwidth stacked DRAM

Hirokazu Ezawa*, Takashi Togasaki, Tatsuo Migita, Soichi Yamashita, Masahiro Inohara, Yasuhiro Koshio, Masatoshi Fukuda, Masahiro Miyata, Kohei Tatsumi

*この研究の対応する著者

研究成果: Article査読

3 被引用数 (Scopus)

抄録

This paper deals with the process integration to produce a high performance processor with a large-scale and high-bandwidth DRAM chip stacked. Ten micrometres pitch Cu redistribution wiring has been implemented on 12 in. DRAM wafers to relocate the Al bond pads where 40 lm pitch SnCu bumps are formed for a large number of I/Os of the memory interface. A phenol-melamine based resin film which is curable at less than 250 °C can be used so as to avert detraction from memory retention yield as well as to insulate the Cu lines, leading to reduction of wafer warpage in an effort to enable fine pitch lithography. In a chip-on-chip joining process, the logic chip is interconnected with the DRAM chip with a less than 1 μm accuracy by mass reflow bonding of the SnCu micro-bumps on both of the chips, revealing the self-aligning effect of the solder bumps. No failures have been observed after reliability stressing on the packaged two-chip stack. The present process integration has been qualified for the mass producing line to provide some merchant LSI devices and will be viable to future generation devices with more chips stacked using through Si via technology.

本文言語English
ページ(範囲)22-32
ページ数11
ジャーナルMicroelectronic Engineering
103
DOI
出版ステータスPublished - 2013 3月

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 原子分子物理学および光学
  • 凝縮系物理学
  • 表面、皮膜および薄膜
  • 電子工学および電気工学

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