TY - GEN
T1 - Process variation estimation using a combination of ring oscillator delay and FlipFlop retention characteristics
AU - Konno, Takuma
AU - Nishizawa, Shinichi
AU - Ito, Kazuhito
N1 - Funding Information:
This work has been partly supported by JSPS KAKENHI JP17K12657. This work is also partly supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc., Cadence Design Systems, Inc., and Menter Graphics, Inc.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/6/12
Y1 - 2018/6/12
N2 - We propose an extraction method of process variation utilizing D-Flip-Flop (DFF) data retention characteristics and Ring Oscillator(RO) oscillation delay. Extracted process variation is modeled as PMOS and NMOS threshold voltage variations. Retention characteristics of the DFF circuit has different sensitivity to threshold voltage variation from the RO circuit. A DFF circuit is newly introduced as a complementary test structure of the conventional RO circuit for process variation extraction. By combining the RO circuit and the DFF circuits, we can accurately estimate the shift of global process variation. The test structure is implemented into silicon chip and the amount of global variation shift is extracted from measured data.
AB - We propose an extraction method of process variation utilizing D-Flip-Flop (DFF) data retention characteristics and Ring Oscillator(RO) oscillation delay. Extracted process variation is modeled as PMOS and NMOS threshold voltage variations. Retention characteristics of the DFF circuit has different sensitivity to threshold voltage variation from the RO circuit. A DFF circuit is newly introduced as a complementary test structure of the conventional RO circuit for process variation extraction. By combining the RO circuit and the DFF circuits, we can accurately estimate the shift of global process variation. The test structure is implemented into silicon chip and the amount of global variation shift is extracted from measured data.
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U2 - 10.1109/ICMTS.2018.8383773
DO - 10.1109/ICMTS.2018.8383773
M3 - Conference contribution
AN - SCOPUS:85049233494
T3 - IEEE International Conference on Microelectronic Test Structures
SP - 97
EP - 101
BT - ICMTS 2018 - Proceedings of the 2018 IEEE International Conference on Microelectronic Test Structures
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 IEEE International Conference on Microelectronic Test Structures, ICMTS 2018
Y2 - 19 March 2018 through 22 March 2018
ER -