Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA

Zhifeng Zhang, Dajiang Zhou, Shihao Wang, Shinji Kimura

研究成果: Conference contribution

抄録

Deep convolutional neural networks (CNNs) are widely used in many computer vision tasks. Since CNNs involve billions of computations, it is critical to reduce the resource/power consumption and improve parallelism. Compared with extensive researches on fixed point conversion for cost reduction, floating point customization has not been paid enough attention due to its higher cost than fixed point. This paper explores the customized floating point for both the training and inference of CNNs. 9-bit customized floating point is found sufficient for the training of ResNet-20 on CIFAR-10 dataset with less than 1% accuracy loss, which can also be applied to the inference of CNNs. With reduced bit-width, a computational unit (CU) based on Quad-Multiplier Packing is proposed to improve the resource efficiency of CNNs on FPGA. This design can save 87.5% DSP slices and 62.5% LUTs on Xilinx Kintex-7 platform compared to CU using 32-bit floating point. More CUs can be arranged on FPGA and higher throughput can be expected accordingly.

元の言語English
ホスト出版物のタイトルASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
出版者Institute of Electrical and Electronics Engineers Inc.
ページ184-189
ページ数6
2018-January
ISBN(電子版)9781509006021
DOI
出版物ステータスPublished - 2018 2 20
イベント23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of
継続期間: 2018 1 222018 1 25

Other

Other23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
Korea, Republic of
Jeju
期間18/1/2218/1/25

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Field programmable gate arrays (FPGA)
Neural networks
Cost reduction
Computer vision
Electric power utilization
Throughput
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

これを引用

Zhang, Z., Zhou, D., Wang, S., & Kimura, S. (2018). Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA. : ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings (巻 2018-January, pp. 184-189). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2018.8297303

Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA. / Zhang, Zhifeng; Zhou, Dajiang; Wang, Shihao; Kimura, Shinji.

ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. 巻 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 184-189.

研究成果: Conference contribution

Zhang, Z, Zhou, D, Wang, S & Kimura, S 2018, Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA. : ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. 巻. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 184-189, 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea, Republic of, 18/1/22. https://doi.org/10.1109/ASPDAC.2018.8297303
Zhang Z, Zhou D, Wang S, Kimura S. Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA. : ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. 巻 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 184-189 https://doi.org/10.1109/ASPDAC.2018.8297303
Zhang, Zhifeng ; Zhou, Dajiang ; Wang, Shihao ; Kimura, Shinji. / Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA. ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. 巻 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. pp. 184-189
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