Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA

Zhifeng Zhang, Dajiang Zhou, Shihao Wang, Shinji Kimura

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Deep convolutional neural networks (CNNs) are widely used in many computer vision tasks. Since CNNs involve billions of computations, it is critical to reduce the resource/power consumption and improve parallelism. Compared with extensive researches on fixed point conversion for cost reduction, floating point customization has not been paid enough attention due to its higher cost than fixed point. This paper explores the customized floating point for both the training and inference of CNNs. 9-bit customized floating point is found sufficient for the training of ResNet-20 on CIFAR-10 dataset with less than 1% accuracy loss, which can also be applied to the inference of CNNs. With reduced bit-width, a computational unit (CU) based on Quad-Multiplier Packing is proposed to improve the resource efficiency of CNNs on FPGA. This design can save 87.5% DSP slices and 62.5% LUTs on Xilinx Kintex-7 platform compared to CU using 32-bit floating point. More CUs can be arranged on FPGA and higher throughput can be expected accordingly.

本文言語English
ホスト出版物のタイトルASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ページ184-189
ページ数6
ISBN(電子版)9781509006021
DOI
出版ステータスPublished - 2018 2 20
イベント23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of
継続期間: 2018 1 222018 1 25

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2018-January

Other

Other23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
国/地域Korea, Republic of
CityJeju
Period18/1/2218/1/25

ASJC Scopus subject areas

  • 電子工学および電気工学
  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計

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