Reconfigurable circuit design based on arithmetic logic unit using double-gate cntfets

Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura, Shigeyoshi Watanabe

研究成果: Article

抜粋

This letter describes a design methodology for an arithmetic logic unit (ALU) incorporating reconfigurability based on doublegate carbon nanotube field-effect transistors (DG-CNTFETs). The design of a DG-CNTFET with an ambipolar-property-based reconfigurable static logic circuit is simple and straightforward using an ambipolar binary decision diagram (Am-BDD), which represents the cornerstone for the automatic pass transistor logic (PTL) synthesis flows of ambipolar devices. In this work, an ALU with 16 functions is synthesized by the design methodology of a DG-CNTFET-based reconfigurable static logic circuit. Furthermore, it is shown that the proposed ALU is much more flexible and practical than a conventional DG-CNTFET-based reconfigurable ALU.

元の言語English
ページ(範囲)675-678
ページ数4
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E97-A
発行部数2
DOI
出版物ステータスPublished - 2014 1 1
外部発表Yes

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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