Reconfigurable fault tolerant binary tree - implementation in two-dimensional arrays and reliability analysis -

Ituso Takanami*, Katsushi Inoue, Takahiro Watanabe

*この研究の対応する著者

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

We propose a reconfiguration scheme of repairing faulty processors where processors on each level of a binary tree are considered to be a linear array in which spare processors are inserted at regular intervals. The switching networks for compensation are regular and comparatively simple. The logic circuits are simple and their switchings for repair are done autonomously. We give a method of embedding the proposed tree architectures into two-dimensional arrays for WSI implementations. The method embeds the PE's from the root to a certain level L0 into a rectangular array, which is called a root module. For levels L(>L0), the linear array on each level is partitioned into subarrays. Such subarrays are called level modules. A binary tree-connected computer with a specified height is constructed by embedding these modules into two-dimensional arrays. Next, for the proposed scheme. We derive the necessary and sufficient condition for reconfigurability. Using the result, we obtain a formula for computing system's reliability. The reliabilities of our systems are compared with those of several systems already known, and the effectiveness of our systems is shown.

本文言語English
ホスト出版物のタイトル1994 IEEE International Conference on Wafer Scale Integration
編集者Mike R. Lea, Stuart Tewksbury
出版社Publ by IEEE
ページ132-142
ページ数11
ISBN(印刷版)0780318501
出版ステータスPublished - 1994 1 1
外部発表はい
イベントProceedings of the 6th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA
継続期間: 1994 1 191994 1 21

出版物シリーズ

名前1994 IEEE International Conference on Wafer Scale Integration

Other

OtherProceedings of the 6th Annual IEEE International Conference on Wafer Scale Integration
CitySan Francisco, CA, USA
Period94/1/1994/1/21

ASJC Scopus subject areas

  • 工学(全般)

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