Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application

Yiqing Huang*, Qin Liu, Satoshi Goto, Takeshi Ikenaga

*この研究の対応する著者

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

In H.264/AVC based integer motion estimation engine, fixed architectures based on full pixel or direct sub-sampling pattern are widely used for HDTV application. However, these architectures suffer from either high complexity or quality loss problems. In this paper, an adaptive sub-sampling based reconfigurable architecture is given out. Firstly, by executing pixel difference analysis, the adaptive sub-sampling scheme which uses three hardware friendly patterns is applied on homogeneous macroblock (MB). Secondly, the related architecture introduces one more pipeline stage to build up configurable partial SAD values so that system performance is enhanced. Thirdly, a two-level pixel data organization scheme is proposed to solve data reuse and hardware utilization problems caused by adaptive algorithm. Moreover, one cross based SAD generation structure is introduced to achieve adaptive output results with less hardware cost. Experimental results show that, the proposed architecture can averagely save 61.71% clock cycles and accomplish twice or four times processing capability for homogeneous MBs. The maximum clock frequency is 208MHz under the TSMC 0.18μm technology in worst case conditions(1.62V, 125°C).

本文言語English
ホスト出版物のタイトルGLSVLSI 2009 - Proceedings of the 2009 Great Lakes Symposium on VLSI
ページ463-468
ページ数6
DOI
出版ステータスPublished - 2009 11 6
イベント19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09 - Boston, MA, United States
継続期間: 2009 5 102009 5 12

出版物シリーズ

名前Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09
国/地域United States
CityBoston, MA
Period09/5/1009/5/12

ASJC Scopus subject areas

  • 工学(全般)

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