Motion estimation and motion compensation in HEVC and similar video codecs involve huge memory traffic in storing and loading reference frames. The resulting memory power composes a significant portion of system energy consumption. This paper presents a memory power reduction framework that losslessly compresses and decompresses reference frames on-the-fly. We first present the architecture that supports the random access of frame data compressed in variable ratios. The latest recompression algorithms and the corresponding VLSI implementation are also introduced. The framework has been implemented in several UHDTV ASIC and FPGA codecs. Experiments under HEVC common test conditions show an average memory traffic reduction of near 60%.
|ホスト出版物のタイトル||2014 IEEE International Conference on Image Processing, ICIP 2014|
|出版社||Institute of Electrical and Electronics Engineers Inc.|
|出版ステータス||Published - 2014 1 28|
ASJC Scopus subject areas
- Computer Vision and Pattern Recognition