The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Redundant via insertion is an effective and recommended method to reduce the yield loss caused by via failures. In this paper, we introduce a redundant via allocation problem for layer partition-based model and solve it using genetic algorithm. The result oflayer partition-based model depends on the partition and processing order of layers. With our redundant via allocation, it can be achieved independent of these factors. In our method, we first construct a graph to represent candidate relations between vias and redundant vias, and conflict relations between redundant vias because of design rule violations. Then the connected components of graph are computed. On each component, we can perform redundant via allocation on the boundaries of any layer partition. Genetic algorithm is used to optimize the allocation strategy. Experiment results show that our method can efficiently improve the redundant via insertion rate.
|ホスト出版物のタイトル||ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC|
|出版ステータス||Published - 2009|
|イベント||2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha|
継続期間: 2009 10 20 → 2009 10 23
|Other||2009 8th IEEE International Conference on ASIC, ASICON 2009|
|Period||09/10/20 → 09/10/23|
ASJC Scopus subject areas