Redundant via insertion based on conflict removal

Jia Liang*, Song Chen, Takeshi Yoshimura

*この研究の対応する著者

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Double-via insertion is an effective and recommended method for improving chip yield and reliability and reducing the yield loss caused by via failures. In this paper we present a genetic algorithm based method to do the double-via insertion for layouts with grid-less or grid-based routing. Design rule violation between redundant via can be represented by a conflict graph whose vertices are redundant vias and edges represent design rule violations. We propose a genetic algorithm based method exploring the optimal removal of some redundant vias to get a conflict-free redundant via set for double via insertion. To reduce the problem size, we will first merge into one vertex (one redundant via) all the connected components that are cliques of the conflict graph. Experiment results show that the effectiveness of the proposed method.

本文言語English
ホスト出版物のタイトルICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
ページ794-796
ページ数3
DOI
出版ステータスPublished - 2010
イベント2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai
継続期間: 2010 11 12010 11 4

Other

Other2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
CityShanghai
Period10/11/110/11/4

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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