The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Double-via insertion is an effective and recommended method for improving chip yield and reliability and reducing the yield loss caused by via failures. In this paper we present a genetic algorithm based method to do the double-via insertion for layouts with grid-less or grid-based routing. Design rule violation between redundant via can be represented by a conflict graph whose vertices are redundant vias and edges represent design rule violations. We propose a genetic algorithm based method exploring the optimal removal of some redundant vias to get a conflict-free redundant via set for double via insertion. To reduce the problem size, we will first merge into one vertex (one redundant via) all the connected components that are cliques of the conflict graph. Experiment results show that the effectiveness of the proposed method.
|ホスト出版物のタイトル||ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings|
|出版ステータス||Published - 2010|
|イベント||2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai|
継続期間: 2010 11 1 → 2010 11 4
|Other||2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology|
|Period||10/11/1 → 10/11/4|
ASJC Scopus subject areas