Region-oriented placement algorithm for coarse-grained power-gating FPGA architecture

Ce Li*, Yiping Dong, Takahiro Watanabe

*この研究の対応する著者

研究成果: Article査読

1 被引用数 (Scopus)

抄録

An FPGA plays an essential role in industrial products due to its fast, stable and flexible features. But the power consumption of FPGAs used in portable devices is one of critical issues. Top-down hierarchical design method is commonly used in both ASIC and FPGA design. But, in the case where plural modules are integrated in an FPGA and some of them might be in sleep-mode, current FPGA architecture cannot be fully effective. In this paper, coarse-grained power gating FPGA architecture is proposed where a whole area of an FPGA is partitioned into several regions and power supply is controlled for each region, so that modules in sleep mode can be effectively power-off. We also propose a region oriented FPGA placement algorithm fitted to this user's hierarchical design based on VPR [1]. Simulation results show that this proposed method could reduce power consumption of FPGA by 38% on average by setting unused modules or regions in sleep mode.

本文言語English
ページ(範囲)314-323
ページ数10
ジャーナルIEICE Transactions on Information and Systems
E95-D
2
DOI
出版ステータスPublished - 2012 2

ASJC Scopus subject areas

  • ソフトウェア
  • ハードウェアとアーキテクチャ
  • コンピュータ ビジョンおよびパターン認識
  • 電子工学および電気工学
  • 人工知能

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