Region oriented routing FPGA architecture for dynamic power gating

Ce Li*, Yiping Dong, Takahiro Watanabe

*この研究の対応する著者

研究成果: Article査読

抄録

Dynamic power gating applicable to FPGA can reduce the power consumption effectively. In this paper, we propose a sophisticated routing architecture for a region oriented FPGA which supports dynamic power gating. This is the first routing solution of dynamic power gating for coarse-grained FPGA. This paper has 2 main contributions. First, it improves the routing resource graph and routing architecture to support special routing for a region oriented FPGA. Second, some routing channels are made wider to avoid congestion. Experimental result shows that 7.7% routing area can be reduced compared with the symmetric Wilton switch box in the region. Also, our proposed FPGA architecture with sophisticated PR can reduce the power consumption of the system implemented in FPGA.

本文言語English
ページ(範囲)2199-2207
ページ数9
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E95-A
12
DOI
出版ステータスPublished - 2012 12月

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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