In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthesis (CTS) for local clock optimization are used so far, but new methodologies are necessary as the technology node advances. In this paper, we study the register placement problem which is a key component of local clock optimization for highperformance circuit design along with local clock distribution. We formulate it as a minimum weighted maximum independent set problem on a weighted conflict graph and propose a novel efficient two-stage heuristic to solve it. To reduce the graph size, techniques based on register flipping and Manhattan circle are also presented. Experiments show that our heuristic can place all registers without overlaps and achieve significant improvement on the total and maximal register movement.
|ホスト出版物のタイトル||Proceedings -Design, Automation and Test in Europe, DATE|
|出版ステータス||Published - 2009|
|イベント||2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 - Nice|
継続期間: 2009 4月 20 → 2009 4月 24
|Other||2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09|
|Period||09/4/20 → 09/4/24|
ASJC Scopus subject areas