Register placement for high-performance circuits

Mei Fang Chiang, Takumi Okamoto, Takeshi Yoshimura

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthesis (CTS) for local clock optimization are used so far, but new methodologies are necessary as the technology node advances. In this paper, we study the register placement problem which is a key component of local clock optimization for highperformance circuit design along with local clock distribution. We formulate it as a minimum weighted maximum independent set problem on a weighted conflict graph and propose a novel efficient two-stage heuristic to solve it. To reduce the graph size, techniques based on register flipping and Manhattan circle are also presented. Experiments show that our heuristic can place all registers without overlaps and achieve significant improvement on the total and maximal register movement.

本文言語English
ホスト出版物のタイトルProceedings -Design, Automation and Test in Europe, DATE
ページ1470-1475
ページ数6
出版ステータスPublished - 2009
イベント2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 - Nice
継続期間: 2009 4 202009 4 24

Other

Other2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
CityNice
Period09/4/2009/4/24

ASJC Scopus subject areas

  • Engineering(all)

フィンガープリント 「Register placement for high-performance circuits」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル