RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.

Masaki Kumanoya; Kazuyasu Fujishima; Hideshi Miyatake; Yasumasa Nishimura; Kazunori Saito; Takayuki Matsukawa; Tsutomu Yoshihara; Takao Nakano

RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.

Masaki Kumanoya, Kazuyasu Fujishima, Hideshi Miyatake, Yasumasa Nishimura, Kazunori Saito, Takayuki Matsukawa, Tsutomu Yoshihara, Takao Nakano

研究成果: Article › 査読

7 被引用数 (Scopus)

抄録

A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

本文言語	English
ジャーナル	IEEE Journal of Solid-State Circuits
巻	SC-20
号	5
出版ステータス	Published - 1985 10
外部発表	はい

ASJC Scopus subject areas

Electrical and Electronic Engineering

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引用スタイル

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AU - Miyatake, Hideshi

AU - Nishimura, Yasumasa

AU - Saito, Kazunori

AU - Matsukawa, Takayuki

AU - Yoshihara, Tsutomu

AU - Nakano, Takao

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AB - A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

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