RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.

Masaki Kumanoya; Kazuyasu Fujishima; Hideshi Miyatake; Yasumasa Nishimura; Kazunori Saito; Takayuki Matsukawa; Tsutomu Yoshihara; Takao Nakano

RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.

Masaki Kumanoya^*, Kazuyasu Fujishima, Hideshi Miyatake, Yasumasa Nishimura, Kazunori Saito, Takayuki Matsukawa, Tsutomu Yoshihara, Takao Nakano

^*この研究の対応する著者

研究成果: Article › 査読

7 被引用数 (Scopus)

抄録

A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

本文言語	English
ジャーナル	IEEE Journal of Solid-State Circuits
巻	SC-20
号	5
出版ステータス	Published - 1985 10
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

他のファイルとリンク

引用スタイル

@article{8d416991703d4d37917a0c040135bce4,

title = "RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.",

abstract = "A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.",

author = "Masaki Kumanoya and Kazuyasu Fujishima and Hideshi Miyatake and Yasumasa Nishimura and Kazunori Saito and Takayuki Matsukawa and Tsutomu Yoshihara and Takao Nakano",

year = "1985",

month = oct,

language = "English",

volume = "SC-20",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.

AU - Kumanoya, Masaki

AU - Fujishima, Kazuyasu

AU - Miyatake, Hideshi

AU - Nishimura, Yasumasa

AU - Saito, Kazunori

AU - Matsukawa, Takayuki

AU - Yoshihara, Tsutomu

AU - Nakano, Takao

PY - 1985/10

Y1 - 1985/10

N2 - A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

AB - A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

UR - http://www.scopus.com/inward/record.url?scp=0022140487&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022140487&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0022140487

VL - SC-20

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 5

ER -

RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.

抄録

ASJC Scopus subject areas

他のファイルとリンク

フィンガープリント

引用スタイル