抄録
A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.
本文言語 | English |
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ジャーナル | IEEE Journal of Solid-State Circuits |
巻 | SC-20 |
号 | 5 |
出版ステータス | Published - 1985 10 |
外部発表 | はい |
ASJC Scopus subject areas
- Electrical and Electronic Engineering