RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.

Masaki Kumanoya*, Kazuyasu Fujishima, Hideshi Miyatake, Yasumasa Nishimura, Kazunori Saito, Takayuki Matsukawa, Tsutomu Yoshihara, Takao Nakano

*この研究の対応する著者

研究成果: Article査読

7 被引用数 (Scopus)

抄録

A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

本文言語English
ジャーナルIEEE Journal of Solid-State Circuits
SC-20
5
出版ステータスPublished - 1985 10
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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