Residue BDD and its application to the verification of arithmetic circuits

研究成果: Conference contribution

7 引用 (Scopus)

抄録

The paper describes a verification method for arithmetic circuits based on residue arithmetic. In the verification, a residue module is attached to the specification and the implementation, and these outputs are compared by constructing BDD's. For the BDD construction without node explosion, we introduce a residue BDD whose width is less than or equal to a modulus. The method is useful for multipliers including C6288.

元の言語English
ホスト出版物のタイトルProceedings - Design Automation Conference
編集者 Anon
出版者IEEE
ページ542-545
ページ数4
出版物ステータスPublished - 1995
外部発表Yes
イベントProceedings of the 32nd Design Automation Conference - San Francisco, CA, USA
継続期間: 1995 6 121995 6 16

Other

OtherProceedings of the 32nd Design Automation Conference
San Francisco, CA, USA
期間95/6/1295/6/16

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

これを引用

Kimura, S. (1995). Residue BDD and its application to the verification of arithmetic circuits. : Anon (版), Proceedings - Design Automation Conference (pp. 542-545). IEEE.

Residue BDD and its application to the verification of arithmetic circuits. / Kimura, Shinji.

Proceedings - Design Automation Conference. 版 / Anon. IEEE, 1995. p. 542-545.

研究成果: Conference contribution

Kimura, S 1995, Residue BDD and its application to the verification of arithmetic circuits. : Anon (版), Proceedings - Design Automation Conference. IEEE, pp. 542-545, Proceedings of the 32nd Design Automation Conference, San Francisco, CA, USA, 95/6/12.
Kimura S. Residue BDD and its application to the verification of arithmetic circuits. : Anon, 編集者, Proceedings - Design Automation Conference. IEEE. 1995. p. 542-545
Kimura, Shinji. / Residue BDD and its application to the verification of arithmetic circuits. Proceedings - Design Automation Conference. 編集者 / Anon. IEEE, 1995. pp. 542-545
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