Restructuring of memory hierarchy in computing system with spintronics-based technologies

Tetsuo Endoh*, Takashi Ohsawa, Hiroki Koike, Takahiro Hanyu, Hideo Ohno

*この研究の対応する著者

研究成果: Conference contribution

30 被引用数 (Scopus)

抄録

The restructuring of today's computer memory hierarchies that are caught in a dilemma between performance gain and power reduction is one of the most promising ways to making the computers much more efficient with much less power. To this end, several possibilities of using NV memories and NV logic with spin-transfer-torque magnetic tunnel junction (STT-MTJ) as levels in new hierarchies are discussed. A new NV-SRAM cell consisting of four transistors and two MTJs (4T-2MTJ) is shown to be a promising candidate for future NV-cache memories. For NV-main memories, we propose a PFET-based 1T-1MTJ cell combined with a new sense amplifier (S/A). A new NV-latch that can be constructed in flip-flops of synchronous core circuits is proposed and the world's fastest 600MHz operation is experimentally demonstrated.

本文言語English
ホスト出版物のタイトル2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
ページ89-90
ページ数2
DOI
出版ステータスPublished - 2012 9月 27
外部発表はい
イベント2012 Symposium on VLSI Technology, VLSIT 2012 - Honolulu, HI, United States
継続期間: 2012 6月 122012 6月 14

出版物シリーズ

名前Digest of Technical Papers - Symposium on VLSI Technology
ISSN(印刷版)0743-1562

Other

Other2012 Symposium on VLSI Technology, VLSIT 2012
国/地域United States
CityHonolulu, HI
Period12/6/1212/6/14

ASJC Scopus subject areas

  • 電子工学および電気工学

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