TY - GEN
T1 - Restructuring of memory hierarchy in computing system with spintronics-based technologies
AU - Endoh, Tetsuo
AU - Ohsawa, Takashi
AU - Koike, Hiroki
AU - Hanyu, Takahiro
AU - Ohno, Hideo
PY - 2012/9/27
Y1 - 2012/9/27
N2 - The restructuring of today's computer memory hierarchies that are caught in a dilemma between performance gain and power reduction is one of the most promising ways to making the computers much more efficient with much less power. To this end, several possibilities of using NV memories and NV logic with spin-transfer-torque magnetic tunnel junction (STT-MTJ) as levels in new hierarchies are discussed. A new NV-SRAM cell consisting of four transistors and two MTJs (4T-2MTJ) is shown to be a promising candidate for future NV-cache memories. For NV-main memories, we propose a PFET-based 1T-1MTJ cell combined with a new sense amplifier (S/A). A new NV-latch that can be constructed in flip-flops of synchronous core circuits is proposed and the world's fastest 600MHz operation is experimentally demonstrated.
AB - The restructuring of today's computer memory hierarchies that are caught in a dilemma between performance gain and power reduction is one of the most promising ways to making the computers much more efficient with much less power. To this end, several possibilities of using NV memories and NV logic with spin-transfer-torque magnetic tunnel junction (STT-MTJ) as levels in new hierarchies are discussed. A new NV-SRAM cell consisting of four transistors and two MTJs (4T-2MTJ) is shown to be a promising candidate for future NV-cache memories. For NV-main memories, we propose a PFET-based 1T-1MTJ cell combined with a new sense amplifier (S/A). A new NV-latch that can be constructed in flip-flops of synchronous core circuits is proposed and the world's fastest 600MHz operation is experimentally demonstrated.
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U2 - 10.1109/VLSIT.2012.6242475
DO - 10.1109/VLSIT.2012.6242475
M3 - Conference contribution
AN - SCOPUS:84866564548
SN - 9781467308458
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 89
EP - 90
BT - 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
T2 - 2012 Symposium on VLSI Technology, VLSIT 2012
Y2 - 12 June 2012 through 14 June 2012
ER -