Robust AES circuit design for delay variation using suspicious timing error prediction

    研究成果: Conference contribution

    抜粋

    This paper proposes a robust AES (advanced encryption standard) circuit for delay variation. In our proposed AES circuit, suspicious timing error prediction circuits (STEPCs) and their associating gating circuit are incorporated into a normal AES circuit to predict timing errors. STEPCs are inserted between inter-module connections and thus we can monitor almost all of the signal paths between registers and effectively prevent timing errors. The simulation results demonstrate that our AES circuit with STEPCs can be overclocked by up to 1.66X with just 8.05% area overheads.

    元の言語English
    ホスト出版物のタイトルProceedings - International SoC Design Conference 2017, ISOCC 2017
    出版者Institute of Electrical and Electronics Engineers Inc.
    ページ101-102
    ページ数2
    ISBN(電子版)9781538622858
    DOI
    出版物ステータスPublished - 2018 5 29
    イベント14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
    継続期間: 2017 11 52017 11 8

    Other

    Other14th International SoC Design Conference, ISOCC 2017
    Korea, Republic of
    Seoul
    期間17/11/517/11/8

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

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  • これを引用

    Yahagi, Y., Yanagisawa, M., & Togawa, N. (2018). Robust AES circuit design for delay variation using suspicious timing error prediction. : Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 101-102). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368789