Scan technology carries the potential risk of being misused as a side channel to leak out the secrets of crypto cores. The existing scan-based attacks could be viewed as one kind of differential cryptanalysis, which takes advantages of scan chains to observe the bit changes between pairs of chosen plaintexts so as to identify the secret keys. To address such a design/test challenge, this paper proposes a robust secure scan structure design for crypto cores as a countermeasure against scan-based attacks to maintain high security without compromising the testability.
|ジャーナル||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|出版物ステータス||Published - 2012 1 1|
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering