Row-redundancy scheme for high-density flash memory

Masaaki Mihara, Takeshi Nakayama, Minoru Ohkawa, Shinji Kawai, Yoshikazu Milyawaki, Yesushi Tereda, Makoto Ohi, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

This paper describes the application of Gray code to the row decoder so that programming before erasure can be done to the defect word lines without incurring area penalty. Using this technique, a 3.3V operation 16Mb CMOS flash memory is fabricated in 0.5μm CMOS technology. The cell is 75ns at 3.3V Vcc. Process parameters and typical characteristics of the 16Mb memory are summarized. A block diagram of the chip is shown. The array is divided into 8 planes. Each plane is divided into four independently erasable 64kB blocks. There are 16 redundant WLs and 128 redundant columns. 65% of the repaired chips are confirmed by the proposed row redundancy system. Although the scheme is proven only by a limited number of devices, it apparently will be useful independent of the line level and the stage of manufacture. A micrograph of this chip is shown.

本文言語English
ホスト出版物のタイトルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
編集者 Anon
Place of PublicationPiscataway, NJ, United States
出版社Publ by IEEE
ページ150-151
ページ数2
ISBN(印刷版)0780318455
出版ステータスPublished - 1994
外部発表はい
イベントProceedings of the 1994 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
継続期間: 1994 2 161994 2 18

Other

OtherProceedings of the 1994 IEEE International Solid-State Circuits Conference
CitySan Francisco, CA, USA
Period94/2/1694/2/18

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Engineering(all)

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