This paper presents a logic synthesis system based on a combined rule-based and algorithmic approach, where not only tables for transformation are described as rules, but also a two-level logic minimization algorithm is registered as one of the rules. A rule interpreter fires these rules using an effective branch and bound technique. Physical constraints such as longest path lengths between registers, fan-in/out and polarity are checked whenever each rule is applied. The system was implemented in the C language on an EWS4800 and a SUN2/160 workstations and has been applied for actual circuits used in production. The results show that the system generates solutions very close to manual implementation. They also show that the system with the logic minimization algorithm produces 20% smaller circuits on the average than in the case where the algorithm was skipped.
|ジャーナル||NEC Research and Development|
|出版ステータス||Published - 1988 10|
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