Scalability and operating voltage of gate/N- overlap LDD in sub-half-micron regime

M. Shimizu*, M. Inuishi, K. Tsukamoto, Y. Akasaka

*この研究の対応する著者

研究成果: Conference article査読

抄録

The scalability of overlap LDD (OL-LDD) and single drain (SD) CMOSFETs is examined with respect to the allowable operating voltage (VDmax) relevant to hot carrier reliability, time-dependent dielectric breakdown (TDDB) reliability, and short channel effects. VDmax is almost independent of the gate oxide thickness. This is because the smaller degradation with thinner gate oxide is counter-balanced with a larger Isub. It is shown that OL-LDD with tox = 7 approximately 9 nm can be operated with 3.3 V. It is concluded that the performance of CMOS devices with OL-LDD is superior to that with SD for LG down to 0.25 μm.

本文言語English
ページ(範囲)47-48
ページ数2
ジャーナルDigest of Technical Papers - Symposium on VLSI Technology
出版ステータスPublished - 1991 12月 1
外部発表はい
イベント1991 Symposium on VLSI Technology - Oiso, Jpn
継続期間: 1991 5月 281991 5月 30

ASJC Scopus subject areas

  • 電子工学および電気工学

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