Scalable VLSI architecture for variable block size integer motion estimation in H.264/AVC

Yang Song*, Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga


研究成果: Article査読

14 被引用数 (Scopus)


Because of the data correlation in the motion estimation (ME) algorithm of H.264/AVC reference software, it is difficult to implement an efficient ME hardware architecture. In order to make parallel processing feasible, four modified hardware friendly ME workflows are proposed in this paper. Based on these workflows. a scalable full search ME architecture is presented, which has following characteristics: (1) The sum of absolute differences (SAD) results of 4 × 4 sub-blocks is accumulated and reused to calculate SADs of bigger sub-blocks. (2) The number of PE groups is configurable. For a search range of M×N pixels, where M is width and N is height, up to M PE groups can be configured to work in parallel with a peak processing speed of N×16 clock cycles to fulfill a full search variable block size ME (VBSME). (3) Only conventional single port SRAM is required, which makes this architecture suitable for standard-cell-based implementation. A design with 8 PE groups has been realized with TSMC 0.18 μm CMOS technology. The core area is 2.13mm × 1.60 mm and clock frequency is 228 MHz in typical condition (1.8 V, 25°C).

ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
出版ステータスPublished - 2006 4月

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学


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