Scaling guideline of DRAM memory cells for maintaining the retention time

Shuichi Ueno*, Yasuo Inoue, Masahide Inuishi

*この研究の対応する著者

研究成果: Conference article査読

9 被引用数 (Scopus)

抄録

We propose the model of junction leakage current of local cells. Our model can well explain voltage, temperature dependence and distribution of the leakage current. This model indicates that interface state is considered to control the leakage current and retention time. Based on our model, we found that decreasing the trap density and the electric field are effective for decreasing the leakage current. Moreover, a guideline of trap density, storage capacitance and electric field is proposed for designing future DRAMs to maintain the retention time.

本文言語English
ページ(範囲)84-85
ページ数2
ジャーナルDigest of Technical Papers - Symposium on VLSI Technology
出版ステータスPublished - 2000 1月 1
外部発表はい
イベント2000 Symposium on VLSI Technology - Honolulu, HI, USA
継続期間: 2000 6月 132000 6月 15

ASJC Scopus subject areas

  • 電子工学および電気工学

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