We propose the model of junction leakage current of local cells. Our model can well explain voltage, temperature dependence and distribution of the leakage current. This model indicates that interface state is considered to control the leakage current and retention time. Based on our model, we found that decreasing the trap density and the electric field are effective for decreasing the leakage current. Moreover, a guideline of trap density, storage capacitance and electric field is proposed for designing future DRAMs to maintain the retention time.
|ジャーナル||Digest of Technical Papers - Symposium on VLSI Technology|
|出版ステータス||Published - 2000 1月 1|
|イベント||2000 Symposium on VLSI Technology - Honolulu, HI, USA|
継続期間: 2000 6月 13 → 2000 6月 15
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