Second-order polynomial expressions for on-chip interconnect capacitance

Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda

    研究成果: Article査読

    2 被引用数 (Scopus)

    抄録

    Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

    本文言語English
    ページ(範囲)3453-3460
    ページ数8
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E88-A
    12
    DOI
    出版ステータスPublished - 2005 12

    ASJC Scopus subject areas

    • 電子工学および電気工学
    • ハードウェアとアーキテクチャ
    • 情報システム

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