Self-compensating power supply circuit for low voltage SOI

Leona Okamura*, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Tsutomu Yoshihara

*この研究の対応する著者

    研究成果: Conference contribution

    抄録

    SOI device is promised to be a mobile and wireless network applications as it has better potential of high speed, low operating voltage and Q-factor. Gate Body directly connected SOI MOSFET suppresses Sees historical effects and is promised technologies that let the logic circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI logic circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing circuitry especially under ultra low voltage.

    本文言語English
    ホスト出版物のタイトルICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007
    ページ1039-1043
    ページ数5
    出版ステータスPublished - 2008
    イベントICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007 - Kokura
    継続期間: 2007 7 112007 7 13

    Other

    OtherICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007
    CityKokura
    Period07/7/1107/7/13

    ASJC Scopus subject areas

    • 電子工学および電気工学

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