Simplified 20-μm pitch vertical interconnection process for 3D chip stacking

Katsuyuki Sakuma*, Noriyasu Nagai, Mikiko Saito, Jun Mizuno, Shuichi Shoji

*この研究の対応する著者

研究成果: Article査読

24 被引用数 (Scopus)

抄録

This paper describes a simplified vertical interconnection process for three-dimensional (3D) chip stacking. The unique feature of this new process is that the conductive filling material in the through-silicon-vias (TSVs), the microbumps, and the interconnection materials are all fabricated in one processing stage. All of the steps can be performed with the same piece of equipment. Prototype chips with 20-μm-pitch vertical interconnections have been demonstrated successfully. By using this technique, 75-μm deep high-aspect-ratio vias can be completely filled without voids using Ni electroplating and uniform 20-μm-pitch microbumps that are 4-μm tall have been fabricated using Sn-Cu electroplating.

本文言語English
ページ(範囲)339-344
ページ数6
ジャーナルIEEJ Transactions on Electrical and Electronic Engineering
4
3
DOI
出版ステータスPublished - 2009 5月

ASJC Scopus subject areas

  • 電子工学および電気工学

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