Simultaneous placement and global routing algorithm for FPGAs

Nozomu Togawa*, Masao Sato, Tatsuo Ohtsuki

*この研究の対応する著者

研究成果: Conference article査読

2 被引用数 (Scopus)

抄録

An FPGA layout algorithm is presented, which deals with placement and global routing simultaneously by fully exploiting its regular structure. It is based on a simple and fast top-down hierarchical bi-partitioning, with placement and global routes represented by positions of logic-blocks and pseudo-blocks, respectively. Experimental results for several benchmark circuits demonstrates its efficiency and effectiveness.

本文言語English
ページ(範囲)483-486
ページ数4
ジャーナルProceedings - IEEE International Symposium on Circuits and Systems
1
出版ステータスPublished - 1994 12 1
イベントProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
継続期間: 1994 5 301994 6 2

ASJC Scopus subject areas

  • 電子工学および電気工学

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