Simultaneous placement and global routing algorithm for FPGAs with power optimization

Nozomu Togawa*, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki

*この研究の対応する著者

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

This paper proposes a simultaneous placement and global routing algorithm for FPGAs with power optimization. The algorithm is based on hierarchical bipartitioning of layout regions and sets of logic-blocks. When bipartitioning a layout region, pseudo-blocks are introduced to preserve connections if there exist connections between bipartitioned logic-block sets. A global route is represented by a sequence of pseudo-blocks. Since pseudo-blocks and logic-blocks can be dealt with equally, placement and global routing are processed simultaneously. The algorithm gives weights to the nets with high switching probabilities and assigns the blocks connected by weighted nets to the same region. Thus their length is shortened and the power consumption of a whole circuit can be reduced. The experimental results demonstrate the effectiveness and efficiency of the algorithm.

本文言語English
ホスト出版物のタイトルIEEE Asia-Pacific Conference on Circuits and Systems - Proceedings
出版社IEEE
ページ125-128
ページ数4
ISBN(印刷版)0780351460
出版ステータスPublished - 1998 12 1
イベントProceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems - Microelectronics and Integrating Systems (IEEE APCCAS-98) - Chiangmai, Thailand
継続期間: 1998 11 241998 11 27

出版物シリーズ

名前IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings

Other

OtherProceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems - Microelectronics and Integrating Systems (IEEE APCCAS-98)
CityChiangmai, Thailand
Period98/11/2498/11/27

ASJC Scopus subject areas

  • 電子工学および電気工学

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