### 抄録

This paper proposes a simultaneous placement and global routing algorithm for FPGAs with power optimization. The algorithm is based on hierarchical bipartitioning of layout regions and sets of logic-blocks. When bipartitioning a layout region, pseudo-blocks are introduced to preserve connections if there exist connections between bipartitioned logic-block sets. A global route is represented by a sequence of pseudo-blocks. Since pseudo-blocks and logic-blocks can be dealt with equally, placement and global routing are processed simultaneously. The algorithm gives weights to the nets with high switching probabilities and assigns the blocks connected by weighted nets to the same region. Thus their length is shortened and the power consumption of a whole circuit can be reduced. The experimental results demonstrate the effectiveness and efficiency of the algorithm.

元の言語 | English |
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ホスト出版物のタイトル | IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings |

出版場所 | Piscataway, NJ, United States |

出版者 | IEEE |

ページ | 125-128 |

ページ数 | 4 |

ISBN（印刷物） | 0780351460 |

出版物ステータス | Published - 1998 |

イベント | Proceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems - Microelectronics and Integrating Systems (IEEE APCCAS-98) - Chiangmai, Thailand 継続期間: 1998 11 24 → 1998 11 27 |

### Other

Other | Proceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems - Microelectronics and Integrating Systems (IEEE APCCAS-98) |
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市 | Chiangmai, Thailand |

期間 | 98/11/24 → 98/11/27 |

### Fingerprint

### ASJC Scopus subject areas

- Electrical and Electronic Engineering

### これを引用

*IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings*(pp. 125-128). Piscataway, NJ, United States: IEEE.

**Simultaneous placement and global routing algorithm for FPGAs with power optimization.** / Togawa, Nozomu; Ukai, Kaoru; Yanagisawa, Masao; Ohtsuki, Tatsuo.

研究成果: Chapter

*IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings.*IEEE, Piscataway, NJ, United States, pp. 125-128, Proceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems - Microelectronics and Integrating Systems (IEEE APCCAS-98), Chiangmai, Thailand, 98/11/24.

}

TY - CHAP

T1 - Simultaneous placement and global routing algorithm for FPGAs with power optimization

AU - Togawa, Nozomu

AU - Ukai, Kaoru

AU - Yanagisawa, Masao

AU - Ohtsuki, Tatsuo

PY - 1998

Y1 - 1998

N2 - This paper proposes a simultaneous placement and global routing algorithm for FPGAs with power optimization. The algorithm is based on hierarchical bipartitioning of layout regions and sets of logic-blocks. When bipartitioning a layout region, pseudo-blocks are introduced to preserve connections if there exist connections between bipartitioned logic-block sets. A global route is represented by a sequence of pseudo-blocks. Since pseudo-blocks and logic-blocks can be dealt with equally, placement and global routing are processed simultaneously. The algorithm gives weights to the nets with high switching probabilities and assigns the blocks connected by weighted nets to the same region. Thus their length is shortened and the power consumption of a whole circuit can be reduced. The experimental results demonstrate the effectiveness and efficiency of the algorithm.

AB - This paper proposes a simultaneous placement and global routing algorithm for FPGAs with power optimization. The algorithm is based on hierarchical bipartitioning of layout regions and sets of logic-blocks. When bipartitioning a layout region, pseudo-blocks are introduced to preserve connections if there exist connections between bipartitioned logic-block sets. A global route is represented by a sequence of pseudo-blocks. Since pseudo-blocks and logic-blocks can be dealt with equally, placement and global routing are processed simultaneously. The algorithm gives weights to the nets with high switching probabilities and assigns the blocks connected by weighted nets to the same region. Thus their length is shortened and the power consumption of a whole circuit can be reduced. The experimental results demonstrate the effectiveness and efficiency of the algorithm.

UR - http://www.scopus.com/inward/record.url?scp=0032218438&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032218438&partnerID=8YFLogxK

M3 - Chapter

SN - 0780351460

SP - 125

EP - 128

BT - IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings

PB - IEEE

CY - Piscataway, NJ, United States

ER -