Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis

Cong Hao, Jian Mo Ni, Hui Tong Wang, Takeshi Yoshimura

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

This paper proposes a simultaneous scheduling and binding approach for resource and interconnect reduction in high-level synthesis. The scheme incorporates the operation scheduling into functional unit (FU) and register binding, targeting the reduction of both resource and interconnect reduction. A simplified weighted and ordered compatibility graph (SWOCG) based binding algorithm is also proposed and runs tens of times faster than the WOCG based binding algorithm. The experimental results show that our proposal achieves 4% to 15% reduction in resource usage and interconnect reduction, and also runs 5X faster compared to previous works.

本文言語English
ホスト出版物のタイトルProceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781479984831
DOI
出版ステータスPublished - 2016 7 19
イベント11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China
継続期間: 2015 11 32015 11 6

Other

Other11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
国/地域China
CityChengdu
Period15/11/315/11/6

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

フィンガープリント

「Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル