Single-chip multiprocessor for smart terminals

Masato Edahiro; Satoshi Matsushita; Masakazu Yamashina; Naoki Nishi

doi:10.1109/MM.2000.865862

Single-chip multiprocessor for smart terminals

Masato Edahiro, Satoshi Matsushita, Masakazu Yamashina, Naoki Nishi

研究成果: Article › 査読

21 被引用数 (Scopus)

抄録

The MP98 low-power, high-performance microprocessor architecture has been described. It supports smart information terminals using single-chip multiprocessor technologies. Its first prototype (code named Merlot) achieved 1 giga instructions/sec at 1 watt. Several basic algorithms such as hashing, sorting, and searching were realized in artificial intelligence on the multithreaded architecture. The multiple control flow execution (MCFE) in MP98 helps compilers extract parallelism from software. Performance estimates for speech recognition application has been presented.

本文言語	English
ページ（範囲）	12-20
ページ数	9
ジャーナル	IEEE Micro
巻	20
号	4
DOI	https://doi.org/10.1109/MM.2000.865862
出版ステータス	Published - 2000 7月
外部発表	はい

ASJC Scopus subject areas

ソフトウェア
ハードウェアとアーキテクチャ
電子工学および電気工学

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10.1109/MM.2000.865862

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Single-chip multiprocessor for smart terminals

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