Single chip VLSI chrominance/luminance separator based on a silicon compiler

T. Miyazaki; T. Nishitani; S. Aikoh; M. Ishikawa; Takeshi Yoshimura; K. Mitsuhashi; M. Furuichi

Single chip VLSI chrominance/luminance separator based on a silicon compiler

T. Miyazaki^*, T. Nishitani, S. Aikoh, M. Ishikawa, Takeshi Yoshimura, K. Mitsuhashi, M. Furuichi

^*この研究の対応する著者

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

The authors present a single-chip VLSI chrominance/luminance (Y/C) separator that is economically fabricated for NTSC TV signals at 13.5-MHz CCIR standard sampling rate. In order to realize compactness and low power dissipation, two FIR filter architectures and a multiplier structure are proposed. A silicon compiler, which uses these structures, also contributes to fast and error-free VLSI development. The Y/C separator chip has 10.4-mm × 11.7-mm die size and attains about 860-MOPS operating speed.

本文言語	English
ホスト出版物のタイトル	ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
編集者	Anon
出版社	Publ by IEEE
ページ	2433-2436
ページ数	4
巻	4
出版ステータス	Published - 1989
外部発表	はい
イベント	1989 International Conference on Acoustics, Speech, and Signal Processing - Glasgow, Scotland 継続期間: 1989 5月 23 → 1989 5月 26

Other

Other	1989 International Conference on Acoustics, Speech, and Signal Processing
City	Glasgow, Scotland
Period	89/5/23 → 89/5/26

ASJC Scopus subject areas

信号処理
電子工学および電気工学
音響学および超音波学

他のファイルとリンク

引用スタイル

Miyazaki, T, Nishitani, T, Aikoh, S, Ishikawa, M, Yoshimura, T, Mitsuhashi, K & Furuichi, M 1989, Single chip VLSI chrominance/luminance separator based on a silicon compiler. in Anon (ed.), ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. vol. 4, Publ by IEEE, pp. 2433-2436, 1989 International Conference on Acoustics, Speech, and Signal Processing, Glasgow, Scotland, 89/5/23.

@inproceedings{a5bd221523a54a2ea1e86550dc0bf3d0,

title = "Single chip VLSI chrominance/luminance separator based on a silicon compiler",

abstract = "The authors present a single-chip VLSI chrominance/luminance (Y/C) separator that is economically fabricated for NTSC TV signals at 13.5-MHz CCIR standard sampling rate. In order to realize compactness and low power dissipation, two FIR filter architectures and a multiplier structure are proposed. A silicon compiler, which uses these structures, also contributes to fast and error-free VLSI development. The Y/C separator chip has 10.4-mm × 11.7-mm die size and attains about 860-MOPS operating speed.",

author = "T. Miyazaki and T. Nishitani and S. Aikoh and M. Ishikawa and Takeshi Yoshimura and K. Mitsuhashi and M. Furuichi",

year = "1989",

language = "English",

volume = "4",

pages = "2433--2436",

editor = "Anon",

booktitle = "ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings",

publisher = "Publ by IEEE",

note = "1989 International Conference on Acoustics, Speech, and Signal Processing ; Conference date: 23-05-1989 Through 26-05-1989",

}

TY - GEN

T1 - Single chip VLSI chrominance/luminance separator based on a silicon compiler

AU - Miyazaki, T.

AU - Nishitani, T.

AU - Aikoh, S.

AU - Ishikawa, M.

AU - Yoshimura, Takeshi

AU - Mitsuhashi, K.

AU - Furuichi, M.

PY - 1989

Y1 - 1989

N2 - The authors present a single-chip VLSI chrominance/luminance (Y/C) separator that is economically fabricated for NTSC TV signals at 13.5-MHz CCIR standard sampling rate. In order to realize compactness and low power dissipation, two FIR filter architectures and a multiplier structure are proposed. A silicon compiler, which uses these structures, also contributes to fast and error-free VLSI development. The Y/C separator chip has 10.4-mm × 11.7-mm die size and attains about 860-MOPS operating speed.

AB - The authors present a single-chip VLSI chrominance/luminance (Y/C) separator that is economically fabricated for NTSC TV signals at 13.5-MHz CCIR standard sampling rate. In order to realize compactness and low power dissipation, two FIR filter architectures and a multiplier structure are proposed. A silicon compiler, which uses these structures, also contributes to fast and error-free VLSI development. The Y/C separator chip has 10.4-mm × 11.7-mm die size and attains about 860-MOPS operating speed.

UR - http://www.scopus.com/inward/record.url?scp=0024937260&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024937260&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0024937260

VL - 4

SP - 2433

EP - 2436

BT - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

A2 - Anon, null

PB - Publ by IEEE

T2 - 1989 International Conference on Acoustics, Speech, and Signal Processing

Y2 - 23 May 1989 through 26 May 1989

ER -

Single chip VLSI chrominance/luminance separator based on a silicon compiler

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ASJC Scopus subject areas

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