Single chip VLSI chrominance/luminance separator based on a silicon compiler

T. Miyazaki, T. Nishitani, S. Aikoh, M. Ishikawa, Takeshi Yoshimura, K. Mitsuhashi, M. Furuichi

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

The authors present a single-chip VLSI chrominance/luminance (Y/C) separator that is economically fabricated for NTSC TV signals at 13.5-MHz CCIR standard sampling rate. In order to realize compactness and low power dissipation, two FIR filter architectures and a multiplier structure are proposed. A silicon compiler, which uses these structures, also contributes to fast and error-free VLSI development. The Y/C separator chip has 10.4-mm × 11.7-mm die size and attains about 860-MOPS operating speed.

本文言語English
ホスト出版物のタイトルICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
編集者 Anon
出版社Publ by IEEE
ページ2433-2436
ページ数4
4
出版ステータスPublished - 1989
外部発表はい
イベント1989 International Conference on Acoustics, Speech, and Signal Processing - Glasgow, Scotland
継続期間: 1989 5 231989 5 26

Other

Other1989 International Conference on Acoustics, Speech, and Signal Processing
CityGlasgow, Scotland
Period89/5/2389/5/26

ASJC Scopus subject areas

  • 信号処理
  • 電子工学および電気工学
  • 音響学および超音波学

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