Small delay fault model for intra-gate resistive open defects

Masayuki Arai*, Akifumi Suto, Katsuyuki Nakano, Michihiro Shintani, Kazuhiko Iwasaki, Kazumi Hatayama, Takashi Aikyo

*この研究の対応する著者

研究成果: Conference contribution

10 被引用数 (Scopus)

抄録

We propose the fault model considering weak resistive opens inside the gate which might cause pattern-sequence-dependent and timing-dependent malfunction of the circuit. We assume the fixed observation interval for the signal transition, and derive the minimum resistance of intra-gate resistive opens to be detected as a fault by SPICE simulation. Based on the simulation results, we establish three fault models, that is, the one considering the location of the resistance, the one considering both the location and the resistance distribution, and the simplified one where str and stf faults considering the signal transition of the input ports are assumed. The coverage calculation for the primitive gates and small benchmark circuit reveals that the proposed models have more accuracy on the detection of weak open defects.

本文言語English
ホスト出版物のタイトルProceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009
ページ27-32
ページ数6
DOI
出版ステータスPublished - 2009
外部発表はい
イベント2009 27th IEEE VLSI Test Symposium, VTS 2009 - Santa Cruz, CA, United States
継続期間: 2009 5月 32009 5月 7

出版物シリーズ

名前Proceedings of the IEEE VLSI Test Symposium

Conference

Conference2009 27th IEEE VLSI Test Symposium, VTS 2009
国/地域United States
CitySanta Cruz, CA
Period09/5/309/5/7

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学

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